1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to methods of forming field effect transistors on a semiconductor substrate.
2. Description of Related Art
Due to demand for smaller and more power-efficient electronic devices, research on methods of increasing semiconductor device integration is actively being pursued. In order to reduce transistor size to meet these demands for higher device integration, increasingly fine transistor patterns may be required. However, as transistor size decreases, a variety of problems may result, such as short channel effects. As such, research is being conducted on fin field-effect transistors (FinFETs), which may reduce short channel effects.
A method of fabricating a Fin FET is disclosed in U.S. Pat. No. 6,642,090 entitled “Fin FET Devices from Bulk Semiconductor and Method for Forming” to Fried, et al., the disclosure of which is hereby incorporated by reference.
FIG. 1 is a cross-sectional view illustrating exemplary methods of fabricating FinFETs as described in U.S. Pat. No. 6,642,090.
Referring to FIG. 1, a semiconductor substrate 200 is formed. Hard mask patterns 224 are formed on the semiconductor substrate 200. The semiconductor substrate 200 is selectively etched using the hard mask patterns 224 as etching masks. As a result, portions of the semiconductor substrate 200 that are exposed by the hard mask patterns 224 are selectively recessed. The portions of the semiconductor substrate 200 that remain after the selective etching process is performed form fins 210. Trenches are formed on either side of each fin 210. Thereafter, the semiconductor substrate 200 including the fins 210 is subjected to an ion implantation process. The fins 210 are protected from the ion implantation due to the hard mask patterns 224 formed thereon. After the ion implantation process, the semiconductor substrate 200 is thermally oxidized to form oxide layers on bottom surfaces of the trenches between the fins 210. During the thermal oxidation process, oxide layers are also formed on sidewalls of the fins 210. The oxide layers on the bottom surfaces of the trenches may be about five times thicker than the oxide layers on the sidewalls of the fins 210. The thicker oxide layers form lower isolation layers 214. An inversion layer channel may be formed in a portion of each fin 210. The width of the inversion layer channel may be defined by the lower isolation layers 214. The oxide layers formed on the sidewalls of the fins 210 are then removed, and gate dielectric layers 220 are formed on the sidewalls of the fins 210. Gate electrodes 222 are then formed on sidewalls and upper surfaces of the fins 210. Drain regions (and drain electrodes) and source regions (and source electrodes) are respectively formed at opposite ends of the fins 210, thereby completing the FinFET.
When a sufficient voltage is applied to the gate electrode 222, an inversion layer channel is formed in the channel region of the fin 210, and current flows between the drain region and the source region. In other words, current flows through the wall-shaped fin 210 in a longitudinal direction. The channel region of the fin 210 may be formed to a width that is less than two times the maximum width of the depletion region. As such, when a voltage less than a threshold voltage of the device is applied to the gate electrode 222, the channel region may become completely depleted, which may improve susceptibility to short channel effects.
However, many semiconductor devices may include a cell array region and a peripheral circuit region in a single wafer. In some instances, it may be advantageous for the cell array region to include transistors, such as FinFETs, that have similar operational characteristics. The peripheral circuit region may include transistors having different operational characteristics. For example, some transistors may be used as differential amplifiers, while others may be used as drivers. In order to obtain such different operational characteristics, channel regions of different sizes may be required. For example, when the width of the channel region is more than twice the maximum depletion width for higher voltages, the channel region may not achieve a complete depletion state. Accordingly, a FinFET may be more susceptible to short channel effects as the width of the channel region (and therefore, the height of the fin) is increased.